Search - dual port RAM

[Communication] code-demo

Description: HM6264Driver_DS HM6264 RAM的读写驱动程序 S480_Manual_C S480的手动播放范例（for SACMV26e.lib） SetIOBit SPCE061A 利用C语言进行软件端口位操作范例 ShowsinTable 简易正弦波发生器方案，同时提供全正数的正弦表 SleepTimerWakeup 定时中断唤醒CPU的范例 UARTDemo 使用UART中断方式进行通讯的范例 UARTDouble UART双机通讯范例，采用中断方式 -HM6264Driver_DS HM6264 RAM read and write drivers for the S480 manual S480_Manual_C broadcast paradigm (for SACMV26e.lib) SetIOBit SPCE061A C language for the use of port-operating software paradigm ShowsinTable simple sine wave generator programs, is to provide the number of regular sine table SleepTimerWakeup CPU interrupt awaken example UARTDemo use UART interrupt communication paradigm UARTDouble Dual UART communications paradigm Interrupt Mode
Platform: | Size: 286073 | Author: 赵孜恺 | Hits:

[Communication] code-demo

Description: HM6264Driver_DS HM6264 RAM的读写驱动程序 S480_Manual_C S480的手动播放范例（for SACMV26e.lib） SetIOBit SPCE061A 利用C语言进行软件端口位操作范例 ShowsinTable 简易正弦波发生器方案，同时提供全正数的正弦表 SleepTimerWakeup 定时中断唤醒CPU的范例 UARTDemo 使用UART中断方式进行通讯的范例 UARTDouble UART双机通讯范例，采用中断方式 -HM6264Driver_DS HM6264 RAM read and write drivers for the S480 manual S480_Manual_C broadcast paradigm (for SACMV26e.lib) SetIOBit SPCE061A C language for the use of port-operating software paradigm ShowsinTable simple sine wave generator programs, is to provide the number of regular sine table SleepTimerWakeup CPU interrupt awaken example UARTDemo use UART interrupt communication paradigm UARTDouble Dual UART communications paradigm Interrupt Mode
Platform: | Size: 285696 | Author: 赵孜恺 | Hits:

[Com Port] 14SPI

Description: c8051f系列单片机的SPI 并行/串行通信源程序 Cygnal出的一种混合信号系统级单片机。片内含CIP－51的CPU内核，它的指令系统与MCS－51完全兼容。其中的C8051F020单片机含有64kB片内Flash程序存储器，4352B的RAM、8个I／O端口共64根I／O口线、一个12位A／D转换器和一个8位A／D转换器以及一个双12位D／A转换器、2个比较器、5个16位通用定时器、5个捕捉／比较模块的可编程计数／定时器阵列、看门狗定时器、VDD监视器和温度传感器等部分。C8051F020单片机支持双时钟，其工作电压范围为2．7～3．6V（端口I/O,RST和JTAG引脚的耐压为5V）。与以前的51系列单片机相比，C8051F020增添了许多功能，同时其可靠性和速度也有了很大提高。 -c8051f Series MCU SPI Parallel/Serial Communication source Cygnal out a single-chip mixed-signal system-level. Tablets containing the CIP-51 core CPU, and its command system and the MCS-51 is fully compatible. Containing one of the C8051F020 single-chip 64kB chip Flash program memory, 4352B of RAM, 8个I/O ports a total of 64 I/O port line, a 12-bit A/D converter and an 8-bit A/D converter as well as a dual 12-bit D/A converter, 2 comparators, five 16-bit general purpose timers, 5 capture/compare module programmable counter/timer arrays, Watchdog Timer, VDD Monitor and temperature sensors and other parts. C8051F020 single-chip dual clock, its operating voltage range of 2.7 ~ 3.6V (Port I/O, RST, and JTAG pins of the voltage to 5V). With the previous 51 series single-chip comparison, C8051F020 added a lot of functionality, reliability and speed at the same time also has been greatly improved.
Platform: | Size: 6144 | Author: 天下第三 | Hits:

[Industry research] Using-the-Virtex-Block-SelectRAMP

Description: The Virtex™ series provides dedicated blocks of on-chip, true dual-read/write port synchronous RAM, with 4096 memory cells. Each port of the block SelectRAM+™ memory can be independently configured as a read/write port, a read port, or a write port, and each port can be configured to a specific data width. The block SelectRAM+ memory offers new capabilities allowing the FPGA designer to simplify designs.-The Virtex™ series provides dedicated blocks of on-chip, true dual-read/write port synchronous RAM, with 4096 memory cells. Each port of the block SelectRAM+™ memory can be independently configured as a read/write port, a read port, or a write port, and each port can be configured to a specific data width. The block SelectRAM+ memory offers new capabilities allowing the FPGA designer to simplify designs.
Platform: | Size: 66560 | Author: asura | Hits:

[VHDL-FPGA-Verilog] IDT7005

Description: 双端口静态RAM的VHDL程序，具体芯片型号为IDT7005-DUAL-PORT STATIC RAM
Platform: | Size: 3373056 | Author: shufengxiong | Hits:

[VHDL-FPGA-Verilog] QuartusII_IP_Core

Description: 以设计双端口RAM为例说明QuartusII中利用免费IP核的设计的详细教程-To design dual-port RAM as an example of the use of a detailed tutorial QuartusII free IP core design
Platform: | Size: 635904 | Author: wisdom | Hits:

[Other] dual_port_ram

Description: True dual port ram VHDL implementation
Platform: | Size: 1024 | Author: slalom | Hits:

[VHDL-FPGA-Verilog] Synchronous-FIFO

Description: FIFO是英文FIRST-IN-FIRST-OUT的缩写，是一种先进先出的数据缓存器，它与普通存储器的区别是没有外部读写地址线，这样使用起来非常方便，但是缺点是只能顺序读写数据，其数据地址由内部读写指针自动加1完成 FIFO的主要功能是基于对双口RAM的读写控制来完成的，根据双口RAM的数据存储状况产生空满信号。双口RAM指的就是能同时对RAM进行读写操作的RAM存储器 -FIFO is an abbreviation of the English FIRST-IN-FIRST-OUT, which is a FIFO data buffer, it is the difference between ordinary memory is no external write address lines, so very convenient to use, but the drawback is that only the order read and write data, the data read by the internal address pointer is automatically incremented by 1 to complete the FIFO main function is based on the dual-port RAM read and write control to complete, resulting in empty status full signal based on data stored in the dual-port RAM. Refers to the dual-port RAM can simultaneously read and write RAM RAM memory
Platform: | Size: 4096 | Author: 刘东辉 | Hits:

[Other] dualporttst-1_1

Description: interfacing dual port ram in vhdl
Platform: | Size: 195584 | Author: franofcholet | Hits:

[VHDL-FPGA-Verilog] Sunhaibo

Description: ＰＣＩ9054的读写，其中包括双口ＲＡＭ，以及寄存器的使用-PCI9054 read and write, which includes dual port RAM, as well as the use of registers
Platform: | Size: 4644864 | Author: 孙悦 | Hits:

[VHDL-FPGA-Verilog] dual_ram

Description: 在ISE中测试双端口RAM的源码，结合DDS可以通过Isim仿真直接测试RAM IP核的使用是否正常。-Dual-port RAM test source code in ISE, the binding DDS RAM IP core can be directly tested whether the use of the normal simulation.
Platform: | Size: 2048 | Author: 唐宏伟 | Hits:

[VHDL-FPGA-Verilog] ram_2

Description: 双端口RAM，可读，可写，用Verilog编写。希望与大神交流，求大神指正。(Dual port RAM, readable and writable, written in Verilog. Hope to communicate with great God, ask God to correct me)
Platform: | Size: 11412480 | Author: 么么哒哈123 | Hits:

[VHDL-FPGA-Verilog] fpga

Description: pid算法控制电机运动，实现fpga与dsp的双口RAM通信(PID algorithm to control motor movement, the realization of FPGA and DSP dual port RAM communication)
Platform: | Size: 13411328 | Author: 峰语 | Hits:

[VHDL-FPGA-Verilog] Memory Verilog

Description: ROM,RAM (dual port)- Verilog
Platform: | Size: 1585 | Author: gsrwork2017@gmail.com | Hits:

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[Communication] code-demo

[Communication] code-demo

[Com Port] 14SPI

[Industry research] Using-the-Virtex-Block-SelectRAMP

[VHDL-FPGA-Verilog] IDT7005

[VHDL-FPGA-Verilog] QuartusII_IP_Core

[Other] dual_port_ram

[VHDL-FPGA-Verilog] Synchronous-FIFO

[Other] dualporttst-1_1

[VHDL-FPGA-Verilog] Sunhaibo

[VHDL-FPGA-Verilog] dual_ram

[VHDL-FPGA-Verilog] ram_2

[VHDL-FPGA-Verilog] fpga

[VHDL-FPGA-Verilog] Memory Verilog

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